Semiconductor integrated circuit devices which are predominant at present comprise an integrated assembly of CMOS (Complementary Metal-Oxide Semiconductor) transistors. The semiconductor integrated circuit device has such a tendency that its power consumption increases as the number of transistors which makes up the semiconductor integrated circuit increases. There has been a strong demand for a reduction in the power consumption of the semiconductor integrated circuit device. With the development in recent years of the low-power CMOS device technology, there has been proposed a power supply control scheme for reducing the power consumption of a semiconductor integrated circuit device by supplying a required minimum power supply voltage to each circuit block of the semiconductor integrated circuit device. For example, T. Kuroda et al. have proposed a power supply control scheme for dynamically controlling a power supply voltage in order to equalize a critical path delay to a lower limit entering a clock cycle in a semiconductor integrated circuit device [T. Kuroda, K. Suzuki, S. Mita, T. Fujita, F. Yamane, F. Sano, A. Chiba, Y. Watanabe, K. Matsuda, T. Maeda, T. Sakurai, and T. Furuyama; “Variable Supply-Voltage Scheme for Low-Power High-Speed CMOS Digital Design,” IEEE Journal of Solid-State Circuits, vol. 33, pp. 454-462, March 1998]. In the semiconductor integrated circuit device to which the scheme of Kuroda et al. is applied, a reference current for controlling a threshold voltage is fixed to a leak current value as a target in a transistor device. Therefore, there is no optimization of the threshold voltage in this semiconductor integrated circuit device.
With semiconductor devices being progressively scaled, the proportion of a leakage power in the total power consumption of a semiconductor device is growing. The leakage power refers to an electric power consumed due to a leakage current in the semiconductor device. K. Nose et al. have reported that it is effective to set the proportion of a leakage power in the total power to 30% at maximum [K. Nose, and T. Sakurai; “Optimization of VDD and VTH for Low-Power and High-Speed Applications,” ASP-DAC, pp. 469-474, January 2000]. The results accomplished by K. Nose et al. are based on a theoretical analysis, and they have not clearly specified how to realize such a semiconductor integrated circuit device.
JP-A-2001-345693 discloses a semiconductor integrated circuit device in which an association table (TBL) representing a combination of clock frequencies, power supply voltages, and substrate bias voltages is prepared in advance, and the clock frequency, power supply voltage, and substrate bias voltage can be controlled by referring to the association table. It should be noted that JP-A-2001-345693 corresponds to the specifications of U.S. Pat. No. 6,774,705 and U.S. Pat. No. 6,943,613.